### Adders

Before understanding the adders, lets first understand the arithmetic circuits that are used in Digital System.

**Arithmetic circuits**

In digital systems, various data processing tasks can be performed. Arithmetic circuits are derived from the combinational logic circuit in which arithmetic operations such as **addition, subtraction, multiplication, complement, shift, increment, decrement, etc., can be performed according to Boolean logi**c. The ease of doing arithmetic tasks captures common people’s attention towards computers, calculators, etc. These devices save a huge amount of time and provide precision and accuracy as well. All the operations performed inside the calculators are performed according to binary addition and subtraction.

### Binary Addition

Before proceeding forward, let’s revise the concept of performing addition or subtraction according to Boolean logic. In any binary number, the left-most digit is MSB, and the rightmost digit is LSB.

MSB | LSB | ||

### Binary addition rules

Binary addition is very simple. Understanding the first three forms given below is very easy. And for the fourth case is 1 + 1 = 10, we write ‘0’ and carry forward ‘1’ to the next significant place value.

0 + 0 = 0

1 + 0 = 1

0 + 1 = 1

1 + 1 = 10

Simple addition | Binary addition | |||||||

5 | 1 | 0 | 1 | |||||

+ | 2 | + | 1 | 0 | ||||

7 | 1 | 1 | 1 |

**Example 1:**

In binary, number ‘5’ is represented as ‘101,’ and number ‘2’ is represented as ’10.’ In binary, place values have weightage starting from unit’s place as 1’s, 2’s, 4’s, 8’s, 16’s, 32’s, 64’s and 128’s.

1 | ||||||||||

1 | 0 | 1 | 0 | 1 | 0 | |||||

+ | 3 | + | 1 | 1 | ||||||

1 | 3 | 1 | 1 | 0 | 1 |

**Example 2:-**

In binary, the number ‘10’ is represented as ‘1010,’ and the number ‘3’ is represented as ’11.’

### Adders in Digital System

In arithmetic, the typical application is the sum of two binary numbers or digits, and to perform this operation, we use Adders.

0 + 0 = 0

1 + 0 = 1

0 + 1 = 1

1 + 1 = 10

Augend Addend

Adder can be classified into two types:

**Half Adder****Full Adder**

### Half-adder

The half adder is a combinational circuit used to perform the a*ddition of two binary inputs and produces the two binary outputs a*s **sum (S) and the carry(C) bits.** The term half-adder leads to the conclusion that **one full-adder can be configured using two half-adders.**

Truth table:-

Inputs | Outputs | ||

A | B | SUM (S) | CARRY OUT (C) |

XOR | AND | ||

0 | 0 | 0 | 0 |

0 | 1 | 1 | 0 |

1 | 0 | 1 | 0 |

1 | 1 | 0 | 1 |

From the above truth table, we can observe that the output S will be equal to ‘1’ when only one of the input variables is ‘1’. And the Carry output C will be equal to ‘1’ only when inputs A and B both are ‘1’ simultaneously. **Also, note that the least significant bit (LSB) is represented by the value of output S.**

K-Map for sum (S): –

B

A 0 1

0 | 1 | |

1 | 1 |

K-Map for output carry (C): –

B

A 0 1

0 | ||

1 | 1 |

### Logic Diagram of Half-Adder

A half adder can be implemented by using one Ex-OR and an AND gate.

The logical expressions for sum and carry are:

S = A’B + AB’ = A ⨁ B and C = AB

### Half adder using universal logic NAND gates

The logical expression for sum and carry are:-

S = A’B + AB’

= A’B + AA’ + AB’ + BB’

= A (A’ + B) + B (A’ + B’)

= A. (AB)’ + B. (AB)’

= ((A. (AB)’)’. (B. (AB)’)’)’

C= AB = ((AB)’)’

The logic diagram of half adder using NAND logic gate:-

Note: – B’ means “complement of B.”

### Half adder using universal logic NOR gates

The logical expression for sum and carry are:-

S = A’B + AB’

= AB’ + AA’ + A’B + BB’

= A (A’ + B) + B (A’ + B’)

= (A +B) (A’ + B’)

= ((A + B)’ + (A’ + B’)’)’

C= AB = ((AB)’)’ = (A’ + B’)’

The logic diagram of half adder using NOR logic gate:-

### Full-adder

It is a type of a combinational circuit in which the **addition of two input bits and a carry-bits are performed and gives the output as a SUM bit and a CARRYOut bit**. So basically, in full adder, *there are three number of inputs and produces two outputs*. The full adder adds the bits **A & B and the carry from the previous column called the carry-in** (C _{input}), and gives output as the **sum bit S and the carry bit called the carry-out (C _{out}.)**

A Sum

Full – Adder |

B

C _{input } C _{out}

**Truth table:**

Inputs | Outputs | |||

A | B | C _{input} | SUM (S) | CARRY Out (C_{OUT}) |

0 | 0 | 0 | 0 | 0 |

0 | 0 | 1 | 1 | 0 |

0 | 1 | 0 | 1 | 0 |

0 | 1 | 1 | 0 | 1 |

1 | 0 | 0 | 1 | 0 |

1 | 0 | 1 | 0 | 1 |

1 | 1 | 0 | 0 | 1 |

1 | 1 | 1 | 1 | 1 |

The outputs in the truth table are obtained by the addition of the three input variables. We can infer using the above truth table that the output S will be equivalent to ‘1’ in the following two cases:-

**Case 1:-** When only one of the inputs is equal to ‘1.’

**Case 2:-** When all three inputs are equivalent to ‘1.’

And the output C_{OUT} will be equal to’1’ when two or three input variables are equal to’1’. Also, note that the least significant bit (LSB) is represented by the value of output S.

K-Map for sum (S): –

BC

A 00 01 11 10

0 | 1 | 1 | ||

1 | 1 | 1 |

K-Map for carry (C): –

BC

A 00 01 11 10

0 | 1 | |||

1 | 1 | 1 | 1 |

The logical expression for sum and carry out are:-

** S** = A’B’C_{INPUT} + A’BC’_{INPUT} + AB’C’_{INPUT} + ABC _{INPUT}

= (AB’ + A’B) C’_{INPUT } + (AB + A’B’) C _{INPUT}

= (A ⨁ B) C ’_{INPUT }+ (A ⨁ B) C_{INPUT}

= A ⨁ B ⨁ C_{INPUT}

**C _{OUT}** = AB + BC + CA

** **= (A⨁ B) C_{INPUT} + AB

Logic Diagram of Full adder using two half-adders is shown below:-

Below is the standard block diagram to demonstrate a full-adder using the dual half-adders:-

**Realization of full-adder in the form of SOP**

The full-adder can also be implemented using the universal gates such as only the NAND gate or only the NOR gate. In total, nine NAND/NOR gates are required to implement it.

### Parallel adder

The parallel adder is a type of combinational circuit used to perform the addition of the binary numbers. It is *designed using the full adders connected in cascade form such that the output carry of each full-adder is joined to the input carry of the subsequent full adder.* It can be extended to add n-bit numbers using the n-full-adders. The parallel adder is also known as “**Ripple- carry adder.”**

In addition,

‘n-bit’ binary parallel adder requires = ‘n’ full-adder

= (n – 1) Full-adder + one half-adder

= (n – 1) {2 half-adder + 1 OR gate} + one half-adder

= (2n – 1) half-adder + (n – 1) OR gate

### Block diagram of 4-bit parallel adder

Let the two 4-bit inputs are A and B such that.

A_{3} | A_{2} | A_{1} | A_{0} | |

+ | B_{3} | B_{2} | B_{1} | B_{0} |

C_{4} | S_{3} | S_{2} | S_{1} | S_{0} |

The (**A) augend bits** and the (**B) addend bits** of the binary number are depicted using subscript such that subscript ‘0’ represents LSB and the ‘3’ represents the MSB. The ‘S’ depicts the sum of the added bits. The four full-adders linked in cascade form are needed to design a four-bit binary adder, and it is necessary that the output carry of the initial full adder is provided as an input carry for the subsequent full adder and so on.

To understand the concept of the 4-bit binary parallel adder, let’s take an example.

The two binary numbers are given as A = 1011 and B = 0011.

Subscript (i) | 3 | 2 | 1 | 0 |

Carry input (C _{i}) | 0 | 1 | 1 | 0 |

Augend (A_{i}) | 1 | 0 | 1 | 1 |

Addend (B_{i}) | 0 | 0 | 1 | 1 |

Sum (S_{i}) | 1 | 1 | 1 | 0 |

Carry output (C_{i+1}) | 0 | 0 | 1 | 1 |

### Application of 4-bit binary parallel adder

- It is used to perform various arithmetic operations.

- By considering the block diagram of the 4-bit parallel adder, if we want to draw a truth table using the traditional method, it will require 2
^{n}entries in the table.

- In the case of 4-bit parallel adder, value of the number of inputs ‘n’ is 9, in total, 512 entries are required. But using the cascade method, we obtain a much simpler and precise conclusion.

### Carry Propagation

In combinational circuit, the input pulse propagates through the various gates before reaching the output end. The total number of gates and the time delay at each gate decide the final propagation time of each pulse as the output of each adder depends on the input carry from the previous adder. At any stage, the value of Sum(S) attains a **steady-state** only after the propagation of input carry is completed.

For example, in above 4-bit parallel adder block diagram, after applying the input variables A_{3} and B_{3}, the value of C_{3} does not attain the steady-state value until the value of C_{2} is not obtained from the previous stage. In similar way, C_{2 }will be on hold until C_{1 }is obtained and so on up to C_{0}.

The carry propagation time plays a major role in the functioning of the adder. **The speed of the addition of two numbers in the adder can be controlled using carry propagation time**. In order to obtain correct outputs, we should allow sufficient time to propagate the input pulse from various gates. Due to the propagation delay of the gate, the parallel adder becomes very slow in the process. There are various techniques that can be applied to reduce the propagation time. A new type of adder known as ** ‘Look ahead carry adder’ is used to reduce the carry propagation time present in the parallel adder**.

Let’s consider two variables, where carry propagate (P) and carry generate (G), such as:-

P_{i} = A_{i }⨁ B_{i}

G_{i} = A_{i }. B_{i}

And the output sum and carry are represented as:-

S_{i} = P_{i }⨁ C_{i}

C_{i + 1} = G_{i }+ P_{i} C_{i}

For each stage, carry output is represented as:-

C_{0} = input carry

C_{1} = G_{0 }+ P_{0} C_{0}

C_{2} = G_{1 }+ P_{1} C_{1} = G_{1 }+ P_{1} (G_{0 }+ P_{0} C_{0}) = G_{1 }+ P_{1} G_{0 }+ P_{1} P_{0} C_{0}

C_{3} = G_{2 }+ P_{2} C_{2} = G_{2 }+ P_{2} (G_{1 }+ P_{1} G_{0 }+ P_{1} P_{0} C_{0}) = G_{2 }+ P_{2} G_{1 }+ P_{2} P_{1} G_{0 }+ P_{2} P_{1} P_{0} C_{0}

From the above expression of C_{3}, we can conclude that C** _{1} **and C

**do not play any role. It means C**

_{2}_{3 }can be propagated simultaneously with C

**and C**

_{2 }**without any delay. Hence, the delay has been reduced using the ‘Look ahead carry adder.’**

_{1}**Logic Diagram of Look ahead carry generator**

**Logic diagram of a 4-bit parallel adder along with Look ahead carry adder**

In the Look ahead carry adder, to add n-bit, it requires **(n + 1) OR gates **and ** **** AND gates**. And to generate the output carry, the circuit of carry requires three logic gates, and for the output sum, it requires four logic gates.

### Difference between the serial adder and parallel adder

Serial Adder | Parallel adder |

It uses shift registers. | It uses registers with parallel loads. |

It involves one full adder and a carry flip-flop. | For the n-bits in a binary number, it requires n-full adders. |

It is a type of a sequential circuit. | If we exclude the register, then the parallel adder is a type of a combinational circuit. |

### BCD adder

The arithmetic operations are performed directly in decimal form in electronic devices such as calculators, computers, etc. For these devices, the adder is implemented in such a way so that the form of input data and the output data remains the same.

In BCD adder, the addition of two numbers in decimal form can be performed easily. The highest value of the input bit in BCD adder is ‘9’ (1001). So the maximum value of the output sum is 19 (=9 + 9 + 1).

In BCD adder, those positions where the sum is less than or equal to ‘9’ (1001) imply that the SUM is in correct form, and there is no further correction required.

But in those positions where SUM is greater than ‘9’ (1001), a correction of ‘6’ (0110) is added to the output SUM, and the generated carry is added to the subsequent decimal position.

In BCD adder, it is necessary to implement the logic to identify the situation when the SUM is greater than ‘9’ (1001).

Let’s understand this by using an example. There are two 4-bit BCD code groups A and B, which are applied at two inputs of the four-bit binary adder and obtained the output as S_{3} S_{2} S_{1} S_{0 }and the carry-out bit C.

Decimal Number | Binary sum | BCD sum | |||||||||||

K | Z_{3} | Z_{2} | Z_{1} | Z_{0} | C | S_{3} | S_{2} | S_{1} | S_{0} | ||||

0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||

1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | |||

2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | |||

3 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | |||

4 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | |||

5 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | |||

6 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | |||

7 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | |||

8 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | |||

9 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | |||

10 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | |||

11 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | |||

12 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | |||

13 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | |||

14 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | |||

15 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | |||

16 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | |||

17 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | |||

18 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | |||

19 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |

`From the above table, we can observe that whenever the binary sum has output carry K=1, a correction is required. Rest six combinations having Z_{3}=1 and either or both Z_{2 }or Z_{1} equal to ‘1’ from 1010 to 1111 also need correction.

The Boolean expression for output carry is represented as:-

C = K + Z_{3} Z_{2 }+ Z_{3} Z_{1}

Please note that whenever the value of C is equal to 1, it is required to add 0110 to the binary sum and gives an output carry for the subsequent stage.

** A BCD adder is used to add two BCD digits and obtain an output as a sum digit in BCD.** It is possible to connect multiple BCD adders in cascade form to perform the addition of two or more decimal numbers. It is necessary that the output carry of the first BCD adder is provided as the input carry for the subsequent adder.

**Block diagram of BCD adder**